An area-time efficient FPGA-implementation of online finite-set model based predictive controllers for flying capacitor inverters

Recently there has been an increase in the use of model-based predictive control (MBPC) for power-electronic converters. Especially for flying-capacitor multilevel converters (FCC) this offers an interesting possibility to simultaneously control output current and the capacitor voltages. The computational burden however is very high and often restrictive for a good implementation. In this paper a time and resource efficient design methodology is presented for the FPGA implementation of FCC MBPC. The control is fully implemented in programmable digital logic. Due to a parallel processing for the three converter phases and a fully pipelined calculation of the prediction stage an area-time efficient implementation is realized. Furthermore, this is achieved by using a high-level design tool. The implementation aspects for 3, 4 and 5-level FC inverters are discussed, with a focus on the 4-level case

Flying-capacitor multilevel converter voltage balance dynamics for pure resistive load

Multilevel converters need voltage balancing to be able to generate an output voltage with high quality. Flying capacitor converter topology has a natural voltage balancing property. Voltage balance dynamics analytical research methods reported to date are essentially based on a frequency domain analysis using double fourier transform. These complicated methods are not truly analytical, which makes an understanding of parameter influence on time constants difficult. In this paper, a straightforward time domain approach based on stitching of switch intervals piece-wise analytical solutions to a DC modulated H-bridge flying capacitor converter is discussed. This method allows to obtain time-averaged discrete and continuous voltage balance dynamics models. Using small-parameter approximation for pure resistive loads, simple and accurate expressions for voltage balance time constants are deduced, revealing their dependence on load parameters, carrier frequency and duty ratio

Self-precharge in single-leg flying capacitor converters

Flying Capacitor (FC) multilevel pulse width modulated (PWM) converters are an attractive choice due to the natural voltage balance property. During start-up of the converter, care has to be taken that the power switches are not exposed to voltage overstress due to uncharged capacitors. A flying capacitor self-precharge technique is proposed which, by making use of natural balancing and a DC-bus rate control, makes the capacitors balance with a zero average load current. The DC-bus rate control depends on the capacitor voltage balance dynamics. The regular PWM natural balancing technique gives good results for even-level single-leg converter self-precharge, for odd-level converters a special switching pattern is necessary

Improved natural balancing with modified phase shifted PWM for single-leg five-level flying-capacitor converters

Flying capacitor converters (FCCs), as most multilevel converter topologies, require a balancing mechanism of the capacitor voltages. FCCs have the valuable property of natural voltage balancing when a special modulation technique is used. The classic methods, like Phase-Shifted Pulse Width Modulation (PS-PWM), result in very slow balancing for some duty ratio ranges. Previous work showed that for a single-leg five-level FCC one time constant is infinite for a zero desired output voltage. In this paper, a modified PS-PWM scheme for a single-leg fivelevel FCC is presented which results in faster balancing over the total duty ratio range. The modified PS-PWM scheme is studied, resulting in an averaged voltage balancing model. This model is verified using simulations and experiments. The modified PS-PWM scheme solves the slow balancing problems of the normal PS-PWM method for odd-level FCCs, while maintaining the passive control property, and it provides a self-precharge capability

FPGA implementation of online finite-set model based predictive control for power electronics

Recently there has been an increase in the use of model based predictive control (MBPC) for power-electronic converters. MBPC allows fast and accurate control of multiple controlled variables for hybrid systems such as a power electronic converter and its load. The computational burden for this control scheme however is very high and often restrictive for a good implementation. This means that a suitable technology and design approach should be used. In this paper the implementation of finite-set MBPC (FS-MBPC) in field-programmable gate arrays (FPGAs) is discussed. The control is fully implemented in programmable digital logic by using a high-level design tool. This allows to obtain very good performances (both in control quality, speed and hardware utilization) and have a flexible, modular control configuration. The feasibility and performance of the FPGA implementation of FS-MBPC is discussed in this paper for a 4-level flying-capacitor converter (FCC). This is an interesting application as FS-MBPC allows the simultaneous control of the output current and the capacitor voltages, yet the high number of possible switch states results in a high computational load. The good performance is obtained by exploiting the FPGA’s strong points: parallelism and pipe-lining. In the application discussed in this paper the parallel processing for the three converter phases and a fully pipelined calculation of the prediction stage allow to realize an area-time efficient implementation

Simple time domain analysis of a 4-level H-bridge flying capacitor converter voltage balancing

Flying Capacitor (FC) multilevel Pulse Width Modulated (PWM) converters are an attractive choice due to the natural balancing property of the capacitor voltages. The balancing can be studied in the time domain, which results in easy to interpret expressions regarding parameter influence. Time domain analysis is normally done by time averaging of the system model over a PWM-period. In this paper a new method is presented starting from the “voltage unbalance” excessive energy which has to be dissipated in the converter load by switching harmonics in the load current. This is applied on a four-level H-bridge converter, which has dynamics of a high order and is normally hard to describe in the dime domain. The proposed method results in time domain parameters exactly describing the behaviour and the balancing of the capacitor voltages of the four-level H-bridge converter